1. Field of the Invention
The present invention relates to a digital television (TV) receiver using a vestigial sideband (VSB) system, and timing recovering apparatus and method for the digital TV receiver.
2. Description of the Related Art
A high definition television (HDTV) is a next-generation digital TV system developed so that a viewer in a living room can feel the impression in a theater as it is. In comparison to a present analog TV, the HDTV has a much better resolution and a wider aspect ratio, and provides a multichannel sound at a level of a compact disc.
In the United States, Europe, and Japan, the standardization of such a digital TV has been expedited by preparing a broadcasting type and standard in their own ways. In the United States, the transmission format adopts the vestigial sideband (VSB) system proposed by Zenith. In a compression format, MPEG is adopted for video compression, and Dolby AC-3 is adopted for audio compression. Also, the display format is prescribed to be compatible with the existing display method.
For digital transmission of video data compressed by the above-described standard, an error correction coding (ECC) is performed on the compressed video data. At this time, in order to facilitate the data recovery at a receiving part, a synchronizing (sync) signal prepared in a prearranged period is inserted between the error-correction-coded data.
The sync signal is briefly classified into two, a data segment sync signal and a field sync signal.
Here, as shown in FIG. 1, one segment is composed of a data segment signal of 4 symbols and data of 828 symbols. One frame is composed of 313 data segments, which are one field sync segment including a training sequence signal, and 312 general data segments.
At a transmission part such as a broadcasting station, a transmitted signal passes through a mapper for changing the power of the signal to a desired power level before it is transmitted. For example, in case of an 8VSB signal for ground broadcasting, the output level of the mapper one among 8-stage symbol values (i.e., amplitude levels) of xe2x88x92168, xe2x88x92120, xe2x88x9272, xe2x88x9224, 24, 72, 120, and 168. Also, according to the prearrangement, the mapper compulsorily prepares and inserts a 4-symbol data segment sync signal among every 828 symbols, and a field sync signal among every 313 data segments. At this time, the prearranged form of the data segment sync signal is 1, xe2x88x921, xe2x88x921, and 1 in logic, and the allocated mapper output levels are xe2x80x98120xe2x80x99 when the sync signal is xe2x80x981xe2x80x99, and xe2x80x98xe2x88x92120xe2x80x99 when the sync signal is xe2x80x980xe2x80x99. In other words, the data segment sync signal has two levels that continuously alternate for each data segment.
FIG. 2a shows an output form of the segment sync signal in the 8VSB transmission system for ground broadcasting, and FIG. 2b shows the low-pass-filtered waveform of the sync signal. The signal actually received in the receiving part is the low-pass-filtered signal.
In the receiving part such as a TV receiver as shown in FIG. 3, when a VSB-modulated radio frequency (RF) signal is received through an antenna, a tuner 101 selects a frequency of a desired channel by tuning, and converts the selected frequency into a intermediate frequency (IF) signal. A frequency phase locked loop (FPLL) section 102 modulates the IF signal outputted from the tuner 101 to I and Q channel signals of a baseband, and locks their frequencies and phases.
The FPLL section 102 is a circuit where a frequency tracking loop and a PLL are integrated, and serves to lock the frequency first, and then locks the phase if the frequency is locked.
An analog-to-digital (A/D) conversion section 103 converts the I channel signal of the FPLL section 102 into 10-bit digital data, and outputs the digital data to a sync signal detection section 104. Here, the Q channel signal is used only for carrier recovery.
The sync signal detection section 104 detects the data segment sync signal, field sync signal, etc., inserted in the transmitted signal using the 10-bit digital data from the A/D converter 103, and outputs the detected signals to an equalization and error correction section 106. The equalization and error correction section 106 performs an equalization with respect to the data segment sync signal, field sync signal, etc., recovered by the sync signal detection section 104 to correct a linear distortion of amplitude that causes an interference among symbols, and a ghost caused by the signal reflected from a building, mountain, etc., using a training signal, corrects errors produced through a transmission channel, and outputs the equalized and error-corrected signal to a video decoder 107. The video decoder 107 decodes the equalized and error-corrected signal by an MPEG algorithm to form a video signal that a viewer can view.
At this time, an advanced television systems committee (ATSC) VSB transmission system of the United States digital TV (DTV) type carries only data on the transmitted signal.
Accordingly, the receiving part as shown in FIG. 3 should use the same clock signal as used for transmission to recover the data. This function is performed by a timing recovery section 105.
According to the currently proposed ATSC standard, the timing recovery is to be performed using the data segment sync signal regularly inserted by the transmission part.
FIG. 4 is a block diagram of a general timing recovery section 105. Referring to FIG. 4, an analog-to-digital conversion (ADC) section 103 converts the input analog I-channel signal into a digital signal, and outputs the digital signal to a segment sync detection section 104-1 of the sync signal detection section 104 and to a timing error detection section 201 of the timing recovery section 105. The segment sync detection section 104-1 detects a position of the segment sync signal from the digital I-channel signal, and produces a timing enable (timen) signal, PWM enable (pwmen) signal, etc., from the detected segment sync signal. At this time, the timen signal is used as an enable signal of the timing error detection section 201 that extracts timing information, and the pwmen signal is used as an enable signal of a pulse width modulation (PWM) section 202 that converts an output of the timing error detection section 201 so that a converted signal can be used in a charging pump 203.
Here, the timing error detection section 201 can be implemented by a quadrature filter. Specifically, the timing recovery section 105 performs the timing recovery only in a segment sync section after detecting the segment sync signal, and the quadrature filter for extracting the timing information operates in the segment sync section.
The output of the timing error detection section 201 is converted into an up/down signal of the following charging pump 203 by the PWM section 202. The output of the charging pump 203 is inputted to a VCXO 205, after passing through a loop filter 204, to control the VCXO 205. The VCXO 205 adjusts an A/D clock outputted to the ADC 103.
As described above, the timing recovery section 105 recovers the timing to be used as the A/D clock of the A/D conversion section 103 using the data segment sync signal detected by the sync detection section 104.
However, the above-described timing recovery method using the circuit of FIG. 4 shows a very weak characteristic if a strong two-symbol-delayed ghost is added to the original signal and inputted. Specifically, FIG. 5a shows a pattern of the data segment sync signal in case that a one-symbol-delayed ghost exists. In this case, the segment sync pattern is maintained. FIG. 5b show a pattern of the data segment sync signal in case that a two-symbol-delayed ghost exists. In this case, the segment sync pattern is distorted due to the two-symbol-delayed ghost applied thereto, and thus, a correlation value between the distorted pattern and the original segment sync pattern inserted in the transmission part cannot be obtained.
In this case, the segment sync section cannot be recognized, and this causes the enable signal of the timing error detection section 201 for detecting the timing error no to be produced. Accordingly, since the timing error cannot be obtained, it cannot be compensated for. If the timing error is not compensated for, it exerts a fatal effect upon the whole performance of the DTV receiver.
Specifically, if the segment sync detection section 104 cannot accurately detect the data segment sync signal, the timing recovery section 105 cannot accurately recover the timing information. Since this timing information is provided as a clock of the A/D conversion section, the data segment sync signal cannot be accurately detected to cause a vicious circle. Also, since the recovery of the data segment sync signal is performed at a front stage of the receiver, the receiver may not operate at all if the recovery of the data segment sync signal is not accurately performed.
Accordingly, the present invention is directed to a digital TV receiver and timing recovering apparatus and method for the digital TV receiver that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a digital TV receiver which can improve the performance of the receiver by preventing the malfunction of timing recovery.
It is another object of the present invention to provide a digital TV receiver and timing recovering apparatus and method for the digital TV receiver which can more stably perform the segment sync signal detection and timing recovery by using not only data inputted through an I channel but also a Q-channel signal through an internal filter for the segment sync signal detection and timing recovery.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims thereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the digital television (TV) receiver comprises a filtering section for extracting a Q-channel signal whose phase is inverted by 90xc2x0 from an input I-channel signal, a segment sync detection section for obtaining a correlation value between the input I-channel signal and a preset segment sync signal form, and a correlation value between the input Q-channel signal and the preset segment sync signal form, and adding and integrating for a predetermined time the two correlation values, the segment sync detection section judging a segment sync section by searching a peak value of integrated values, and outputting a control signal for informing recovery of the segment sync signal, and a timing recovery section for operating in accordance with the control signal provided from the segment sync detection section, and performing a timing recovery by extracting timing error information from the I-channel signal and the Q-channel signal.
Preferably, the filtering section comprises a Hilbert filter for inverting a phase of the input I-channel signal by 90xc2x0.
The segment sync detection section comprises a first correlation section for obtaining the correlation value between the input I-channel signal and the segment sync signal form (1, xe2x88x921, xe2x88x921, 1) of the preset I-channel signal, a second correlation section for obtaining the correlation value between the Q-channel signal outputted from the filtering section and the segment sync signal form (1, xe2x88x921) of the preset Q-channel signal, an adder for adding the correlation values of the first and second correlation sections, an accumulation section for discriminating a data section and a segment sync section by accumulating outputs of the adder in the unit of one data segment section, and a signal generation section for judging the segment sync section from outputs of the accumulation section, and outputting the control signal for informing the recovery of the segment sync signal.
The timing recovery section comprises a first timing error detection section for operating in accordance with the control signal provided from the segment sync detection section, and extracting the timing error information from the I-channel signal, a second timing error detection section for operating in accordance with the control signal provided from the segment sync detection section, and extracting the timing error information from the Q-channel signal, an adder for adding outputs of the first and second timing error detection sections, a signal conversion section for operating in accordance with the control signal provided form the segment sync detection section, converting an output of the adder into an up/down signal, and outputting the up/down signal to a charging pump, a loop filter for passing therethrough only a low band signal component among the timing error information outputted from the charging pump of the signal conversion section, and a voltage controlled oscillator for recovering the timing by converting its output frequency in accordance with the low band component of the timing error.
In another aspect of the present invention, there is provided a sync signal detecting apparatus for a digital television receiver comprising a first correlation section for obtaining a correlation value between an input I-channel signal and a segment sync signal form of a preset I-channel signal, a filtering section for extracting a Q-channel signal whose phase is inverted by 90xc2x0 from the I-channel signal, a second correlation section for obtaining a correlation value between the Q-channel signal and a segment sync signal form of a preset Q-channel signal, an accumulation section for adding the correlation values of the first and second correlation sections, and repeating for several data segment sections accumulation of added correlation values in a predetermined unit, and a signal generation section for judging that a position where a peak value is continually detected for the several data segment sections is the segment sync section, and outputting a control signal for informing recovery of the segment sync signal.
In still another aspect of the present invention, there is provided a timing recovering apparatus for a digital television receiver comprising a filtering section for extracting a Q-channel signal whose phase is inverted by 90xc2x0 from an input I-channel signal, a timing error detection section for operating in accordance with a control signal provided from a segment sync detection section, and extracting timing error information from the I-channel signal and the Q-channel signal, a signal conversion section for operating in accordance with the control signal provided from the segment sync detection section, converting an output of the timing error detection section into an up/down signal, and outputting the up/down signal to a charging pump, a loop filter for passing therethrough only a low band signal component among the timing error information outputted from the charging pump of the signal conversion section, and a voltage controlled oscillator for recovering the timing by converting its output frequency in accordance with the low band component of the timing error.
In still another aspect of the present invention, there is provided a segment sync signal detection and timing recovery method for a digital television receiver comprising the step of (a) extracting a Q-channel signal whose phase is inverted by 90xc2x0 from an input I-channel signal, (b) obtaining a correlation value between the input I-channel signal and a preset segment sync signal form and a correlation value is between the input Q-channel signal and the preset segment sync signal form, adding and integrating for a predetermined time the two correlation values, judging a segment sync section by searching a peak value of integrated values, and outputting a control signal for informing recovery of the segment sync signal, and (copyright) operating in accordance with the control signal provided at step (b), and performing a timing recovery by extracting timing error information from the I-channel signal and the Q-channel signal.